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<description><![CDATA[TL;DR PyTorch Conference North America 2026 features vLLM across sessions on KV cache management and disaggregated serving, hardware portability, kernel optimization, PyTorch integration, Mixture-of-Experts inference, attention, and production serving. vLLM...]]></descript…+
<content:encoded><![CDATA[<h3><b>TL;DR</b></h3>+
<p>PyTorch Conference North America 2026 features vLLM across sessions on KV cache management and disaggregated serving, hardware portability, kernel optimization, PyTorch integration, Mixture-of-Experts inference, attention, and production serving.</p>+
<h3><b>vLLM at #PyTorchCon NA</b></h3>+
<p><span style="font-weight: 400;">PyTorch Conference North America 2026 comes to San Jose, CA, October 20–21, with technical talks, live demos, lightning talks, sponsored sessions, a keynote, and a Birds of a Feather discussion featuring vLLM.</span></p>+
<p>Across the program, vLLM appears in sessions on serving architecture and KV cache work, hardware portability, kernel and performance optimization, and PyTorch integration. Additional sessions cover Mixture-of-Experts inference, attention, production deployment, broader application stacks, and ope…+
<p><a href="https://hubs.ly/Q04tDx8f0"><span style="font-weight: 400;">View the full conference schedule</span></a></p>+
<p><a href="https://hubs.ly/Q04tDw_W0"><span style="font-weight: 400;">Register for PyTorch Conference North America 2026</span></a></p>+
<h3><strong data-start="1641" data-end="1701">Serving Architecture, KV Cache, and Production Inference</strong></h3>+
<h4><b>A Developer’s Guide to Attention in vLLM</b></h4>+
<p><b>Lucas Wilkinson, Red Hat; Matthew Bonanni, Red Hat</b><b><br />+
</b><b>October 20, 11:45 a.m.–12:10 p.m. | LL20AB | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session explains how vLLM represents, serves, and optimizes attention as models adopt approaches including sliding windows, sparsity, compression, linear variants, and hybrid attention.</span></p>+
<p><span style="font-weight: 400;">The speakers cover attention backends, KV-cache connectors, and the hybrid memory allocator, along with a recent overhaul of vLLM’s attention abstractions, what changed, and how the new design makes emerging architectures easier and cleaner to support.</span></p>+
<h4><b>State-of-the-Art KV Transfer for Disaggregated LLM Serving in vLLM</b></h4>+
<p><b>Nicolò Lucchesi, Mistral AI; Sunita Nadampalli, Amazon; Zhanqiu Hu, Red Hat</b><b><br />+
</b><b>October 20, 2:15–2:40 p.m. | LL20CD | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session covers developments in vLLM’s disaggregated serving stack for transferring KV cache between prefill and decode. Topics include hybrid-model transfer with heterogeneous tensor parallelism, bidirectional KV transfer, the KV Push connector, and KV cache l…+
<p><span style="font-weight: 400;">The speakers report that KV Push reduces time to first token and that, on Nemotron, disaggregated prefill/decode Pareto-dominates co-located serving across concurrency levels.</span></p>+
<h4><b>Native Tiered KV Cache Offloading in vLLM: From Storage Offloading to Disaggregated Serving</b></h4>+
<p><b>Or Ozeri, IBM</b><b><br />+
</b><b>October 20, 2:50–3:15 p.m. | LL20CD | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This talk presents vLLM’s native tiered KV cache offloading framework, newly integrated upstream with no external dependencies.</span></p>+
<p><span style="font-weight: 400;">The framework routes transfers through CPU memory as a universal transport hub. The design minimizes GPU transfer overhead, consolidates I/O through a CPU buffer, avoids specialized transfer APIs, and remains independent of KV cache memory layout across hardware, a…+
<h4><b>LMCache: a cluster-wide open source solution for LLM prompt caching</b></h4>+
<p><b>Kuntai Du, Tensormesh, Inc.</b><b><br />+
</b><b>October 20, 3:40–3:50 p.m. | LL20CD | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">LMCache provides prompt caching across inference engines including vLLM, SGLang, and TensorRT-LLM and storage systems including Mooncake, Redis, and AWS S3.</span></p>+
<p><span style="font-weight: 400;">The session includes a tutorial on deploying LMCache in Kubernetes along with the techniques and research behind its prompt-caching approach.</span></p>+
<h4><b>vLLM KV Cache Management for Model-Specific Requirements</b></h4>+
<p><b>Mengqing Cao, Huawei</b><b><br />+
</b><b>October 20, 5:30–5:40 p.m. | LL20CD | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This session addresses KV cache requirements that vary across model architectures including MLA, SWA, Eagle, and DeepSeek-V4.</span></p>+
<p><span style="font-weight: 400;">It proposes a model-customized KV Cache Planner built around a default planner plus model-specific planners for requirements such as spec grouping, block-size derivation, cache tensor creation, and </span><span style="font-weight: 400;">max_model_len</span><span st…+
<h4><b>Elastic Expert Parallelism in vLLM</b></h4>+
<p><b>Itay Alroy, NVIDIA</b><b><br />+
</b><b>October 21, 2:50–3:15 p.m. | LL20CD | Breakout Session</b></p>+
<p><span style="font-weight: 400;">Elastic Expert Parallelism enables vLLM deployments to add or remove workers at runtime and redistribute experts across the updated worker set with minimal interruption to serving.</span></p>+
<p><span style="font-weight: 400;">The session covers communication reconfiguration, CUDA Graph recapture, expert rebalancing through the EP Load Balancer, weight transfer to new GPUs, and coordination with model forward execution. It also covers how NIXL EP enables grow and shrink operations under …+
<h4><b>Prefix Caching for Autoregressive Stages in Multi-Stage Pipelines</b></h4>+
<p><b>Ricardo Noriega, Red Hat; Alex Brooks, Red Hat</b><b><br />+
</b><b>October 21, 4:20–4:45 p.m. | LL20AB | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This talk explores Automatic Prefix Caching for Stage Outputs in vLLM-Omni, an approach for extending vLLM’s prefix caching to multi-stage models while minimizing GPU memory cost.</span></p>+
<p><span style="font-weight: 400;">The approach aligns external CPU tensor caches with vLLM’s native block management. The speakers also describe how vLLM-Omni dynamically discovers cacheable tensors without requiring manual configuration.</span></p>+
<h3><b>Hardware Portability and Accelerator Backends</b></h3>+
<h4><b>Sponsored: Unifying Open Source LLM Serving on Google Cloud TPUs with TorchTPU</b></h4>+
<p><b>Rob Mulla, Google</b><b><br />+
</b><b>October 20, 10:40–10:50 a.m. | Community Expo | Demo Theater</b></p>+
<p><span style="font-weight: 400;">This 10-minute demo shows TorchTPU’s native, high-performance compilation path for PyTorch models on Cloud TPUs.</span></p>+
<p><span style="font-weight: 400;">The demo highlights TorchTPU as a unified backend for inference engines including vLLM and SGLang, enabling model deployment through those serving engines with minimal code modifications.</span></p>+
<h4><b>Sponsored: PyTorch Ecosystem Running Natively on Trainium</b></h4>+
<p><b>Maen Suleiman, Amazon Web Services</b><b><br />+
</b><b>October 20, 10:55–11:05 a.m. | Community Expo | Demo Theater</b></p>+
<p><span style="font-weight: 400;">This live demo covers PyTorch workflows on Trainium through TorchNeuron, including training with TorchTitan or Hugging Face Transformers v5, serving with vLLM-Neuron, profiling with Neuron Explorer, and adding NKI kernels directly to PyTorch code.</span></p>+
<p><span style="font-weight: 400;">The session also demonstrates Neuron Agentic Development, AI-assisted tooling for kernel authoring and optimization.</span></p>+
<h4><b>One Model Definition, Many Accelerators: Scaling vLLM Across Hardware Without Forks</b></h4>+
<p><b>Thomas Parnell, IBM; Richard Zou, Meta</b><b><br />+
</b><b>October 20, 4:20–4:45 p.m. | LL20CD | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This talk presents hardware-agnostic model definitions for vLLM, an approach that separates model logic from hardware execution paths so the same model definition can run across accelerators without forks or per-platform maintenance.</span></p>+
<p><span style="font-weight: 400;">The design relies on compatibility with </span><span style="font-weight: 400;">torch.compile</span><span style="font-weight: 400;">, well-defined extensibility hooks, and isolation from hardware-specific paths. The speakers show how the approach supports Intel Gaud…+
<h4><b>Portable PyTorch Across AI Accelerators: A Triton Operator Stack from Eager Mode to vLLM</b></h4>+
<p><b>Yonghua Lin, Beijing Academy of Artificial Intelligence</b><b><br />+
</b><b>October 20, 4:55–5:20 p.m. | LL20CD | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session presents FlagOS, an open source system stack using a Triton-based operator, compiler, and runtime layer for PyTorch.</span></p>+
<p><span style="font-weight: 400;">FlagGems implements PyTorch eager-mode operators and LLM-critical kernels in Triton, while the same operator layer connects to vLLM through the </span><span style="font-weight: 400;">vllm-plugin-fl</span><span style="font-weight: 400;"> multi-backend plugin.</span>…+
<p>The speakers report testing FlagOS on 20+ AI chips and architectures and say it has enabled Day-0 adaptation of models including Qwen3.5, MiniMax-M3, MiniCPM-5, and DeepSeek-V4. They report 5–40% inference performance improvement over original vendor adaptation.</p>+
<h4><b>Efficient MoE LLM Inference on Arm with vLLM and OpenVINO</b></h4>+
<p><b>Abhishek Jain, Fujitsu Research of India; N Maajid Khan, Fujitsu Research of India</b><b><br />+
</b><b>October 20, 4:55–5:05 p.m. | LL21ABC | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk presents a vLLM and OpenVINO inference stack optimized for Arm CPUs, including SVE-optimized SDPA and Paged Attention, U8 KV-cache quantization, operator fusion, KleidiAI integration, and optimized threading for 8-bit and 4-bit inference.</span></p>+
<p><span style="font-weight: 400;">For Mixture-of-Experts models, the speakers introduce a NUMA-aware GatherMatMul operator that combines dynamic token and expert selection with matrix multiplication. Benchmarks on AWS Graviton3e show approximately 2x throughput on GPTOSS/Llama models.</span></p>+
<h4><b>Integrating the IBM Spyre Accelerator</b></h4>+
<p><b>David Grove, IBM; Antoni Viros i Martin, IBM Research; Avery Blanchard, IBM Research</b><b><br />+
</b><b>October 20, 4:55–5:20 p.m. | LL21DEF | Breakout Session</b></p>+
<p><span style="font-weight: 400;">Torch-Spyre is an open source project that provides a PyTorch PrivateUse1 device with OpenReg, including an Inductor backend, for the IBM Spyre Accelerator.</span></p>+
<p><span style="font-weight: 400;">The speakers report that the IBM Spyre Accelerator can now run thousands of models from Hugging Face and vLLM through its PyTorch integration. The session covers the state of Torch-Spyre, functional enablement and performance improvements made in 2026, contribution…+
<h4><b>Keynote: Workload Fungibility in the Age of Agents</b></h4>+
<p><b>Bill Jia, Google Cloud</b><b><br />+
</b><b>October 21, 9:15–9:25 a.m. | Grand Ballroom | Keynote</b></p>+
<p><span style="font-weight: 400;">This keynote uses TorchTPU to show PyTorch workflows across model development, training, and serving, including serving through vLLM and SGLang.</span></p>+
<p><span style="font-weight: 400;">The session also demonstrates agentic workflows for moving model workloads from GPUs to TPUs and explores their use for performance optimization tasks including quantization, custom kernel generation, and sharding strategies.</span></p>+
<h4><b>PyTorch-Native LLM Serving on TPU: SGLang and vLLM</b></h4>+
<p><b>Colin Taylor, Meta; Qi Zhou, Google; Angela Yi, Meta</b><b><br />+
</b><b>October 21, 2:15–2:40 p.m. | LL20CD | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session presents SGLang and vLLM running on TPUs through a new PyTorch-native TPU backend while preserving the serving engines’ schedulers, batching systems, OpenAI-compatible APIs, and </span><span style="font-weight: 400;">torch.compile</span><span style="fo…+
<p><span style="font-weight: 400;">The speakers cover </span><span style="font-weight: 400;">torch.compile</span><span style="font-weight: 400;"> lowering to TPU, Pallas attention, tensor and expert parallelism, Mixture-of-Experts execution, FP8 for large MoE models including Qwen3-Coder-480B, multi…+
<h3>Kernel and Performance Optimization</h3>+
<h4><b>High-Velocity GPU Kernel Authoring with CUTLASS Python</b></h4>+
<p><b>Michael Goldfarb, NVIDIA; Guray Ozen, NVIDIA</b><b><br />+
</b><b>October 20, 12:20–12:45 p.m. | 210BF | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This talk presents new Python-first capabilities for CUTLASS CuTe DSL, which the speakers report has delivered high-performance GPU kernels in projects including FlashAttention 4, TRT-LLM, vLLM, and FlashInfer.</span></p>+
<p><span style="font-weight: 400;">The session introduces CuTe DSL extensions, CUTLASS Python Primitives for direct access to low-level hardware instructions, and the Resource and Task Scheduler, a zero-cost metaprogramming framework for static verification of asynchronous primitives.</span></p>+
<h4><b>Faster LLM Serving Startup with fastsafetensors</b></h4>+
<p><b>Takeshi Yoshimura, IBM</b><b><br />+
</b><b>October 20, 3:25–3:35 p.m. | LL20CD | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk presents fastsafetensors, an open source library for accelerating safetensors checkpoint loading in PyTorch inference systems including vLLM.</span></p>+
<p><span style="font-weight: 400;">fastsafetensors removes per-tensor copies, coalesces fragmented I/O, and skips host staging. The speakers report 4.8x to 7.5x faster model loading and up to 28 GB/s of NVMe read throughput.</span></p>+
<p><span style="font-weight: 400;">The session also covers contributions including parallel loading, 3FS integration, ROCm support, a universal wheel with runtime CUDA/ROCm detection, Windows DirectStorage exploration, and unified-memory support.</span></p>+
<h4><b>Sponsored: Quantization Showdown: PyTorch Inference Optimization</b></h4>+
<p><b>Markell Rawls, Red Hat</b><b><br />+
</b><b>October 20, 4:10–4:20 p.m. | Community Expo | Demo Theater</b></p>+
<p><span style="font-weight: 400;">This live demo examines quantization and speculative decoding using tools including LLM Compressor and vLLM.</span></p>+
<p><span style="font-weight: 400;">The session stress-tests the techniques under load to examine the performance, cost, and quality tradeoffs involved in production deployments.</span></p>+
<h4><b>From Weeks to Overnight: Autonomous Day-0 Kernel Bring-Up with Agent Pipelines</b></h4>+
<p><b>Xiaogang Gu, Intel; Qun Yang, Intel</b><b><br />+
</b><b>October 20, 5:30–5:40 p.m. | 210BF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This session presents a pipeline-driven autonomous system for GPU kernel optimization, with specialized agents handling profiling, analysis, code generation, verification, fixes, benchmarking, and evaluation in isolated contexts.</span></p>+
<p><span style="font-weight: 400;">Using real vLLM inference workloads, the speakers report reducing kernel bring-up and optimization cycles from weeks to overnight unattended runs.</span></p>+
<h4><b>Making vLLM Faster on Intel GPUs with Triton Kernels</b></h4>+
<p><b>Whitney Tsang, Intel; Artur Fierka, Intel</b><b><br />+
</b><b>October 21, 12:20–12:30 p.m. | 210BF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk examines Triton kernels for vLLM on Intel GPUs and where Triton can outperform SYCL on inference workloads.</span></p>+
<p><span style="font-weight: 400;">The speakers focus on unified attention, fused MoE, batched MoE, autotuning, tensor-descriptor-oriented kernel structure, and fusion opportunities. They also discuss where these choices improve end-to-end vLLM throughput and latency and where SYCL remains competiti…+
<h4><b>HiFloat: Democratizing Ultra-Low Precision Training and Inference in PyTorch Ecosystems</b></h4>+
<p><b>Yun Zhao, Huawei; Haonan Zhang, Huawei</b><b><br />+
</b><b>October 21, 2:50–3:00 p.m. | LL20AB | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This session introduces HiFloat8 and HiFloat4 and demonstrates HiFloat-accelerated LLM workflows within DeepSpeed and vLLM.</span></p>+
<p><span style="font-weight: 400;">The implementation uses PyTorch custom ops, Triton-based kernels, and </span><span style="font-weight: 400;">torch.compile</span><span style="font-weight: 400;">. In the benchmarks presented, the speakers report that HiF8 achieves final-loss parity with FP16 while …+
<h4><b>Portable Paged Attention: From Triton to Helion</b></h4>+
<p><b>Burkhard Ringlein, IBM Research</b><b><br />+
</b><b>October 21, 3:25–3:50 p.m. | 210BF | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session compares Triton and Helion implementations of Paged Attention and presents an experimental Helion attention backend for vLLM.</span></p>+
<p><span style="font-weight: 400;">The speaker covers differences between the two implementations, algorithm changes needed to achieve matching performance, and optimizations enabled by Helion. Early results indicate that the experimental Helion backend can reduce latency by up to 50% and improve en…+
<h3>PyTorch Integration and Compatibility</h3>+
<h4><b>Shipping PyTorch and Its Ecosystem: A Modern Release Story</b></h4>+
<p><b>Andrey Talman, Meta</b><b><br />+
</b><b>October 20, 11:45–11:55 a.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk covers changes to PyTorch release engineering, including continuous validation of Triton and vLLM against PyTorch nightlies so ecosystem breakage can surface upstream before the release branch is cut.</span></p>+
<p><span style="font-weight: 400;">The session also covers a faster, more predictable release process and the use of AI agents to triage CI, separate noise from regressions, and draft fixes, while leaving final decisions with people.</span></p>+
<h4><b>Sponsored: Making Enterprise Agentic Inference Production-Ready with PyTorch and vLLM</b></h4>+
<p><b>Joseph Groenenboom, Red Hat; Tyler Michael Smith, Red Hat</b><b><br />+
</b><b>October 20, 3:25–3:50 p.m. | LL21ABC | Sponsored Session</b></p>+
<p><span style="font-weight: 400;">This session examines reliability, observability, KV cache management, and concurrency requirements for enterprise inference systems.</span></p>+
<p><span style="font-weight: 400;">The speakers cover a sample of upstream work across PyTorch, vLLM, other Foundation projects, and the broader ecosystem, from core PyTorch build infrastructure to model-serving improvements for tool calling and long-context, multi-turn chat.</span></p>+
<h4><b>Clearing the Path Towards an ABI Stable PyTorch C++ Extension Ecosystem</b></h4>+
<p><b>Sean McGovern, Red Hat; Chris Leonard, Red Hat; Jane Xu, Meta</b><b><br />+
</b><b>October 21, 2:15–2:40 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">PyTorch’s stable ABI provides a binary-compatible C interface that extensions can target across PyTorch versions without recompilation.</span></p>+
<p><span style="font-weight: 400;">This session presents tools for identifying and inventorying unstable API usage and applying source-to-source conversion with LLM-assisted follow-up. The speakers demonstrate the process on libraries including vLLM and SGLang.</span></p>+
<h4><b>From Backed to Unbacked: Sound, Predictable, and Controllable Dynamic Shapes in PyTorch</b></h4>+
<p><b>Laith Sakka, Meta</b><b><br />+
</b><b>October 21, 4:20–4:45 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This talk covers unbacked dynamic shapes for explicit graph-capture workflows including vLLM, export, and pre-compilation, as well as JIT deployments where dynamic-shape recompilation is not acceptable.</span></p>+
<p><span style="font-weight: 400;">The session covers data-dependent errors and branching, work to close the performance gap with backed shapes across TorchBench and vLLM, and APIs for shape constraints and dispatch across compiled artifacts.</span></p>+
<h3><b>vLLM in Broader Applications and Infrastructure</b></h3>+
<h4><b>Understanding Modern Vision Language Models</b></h4>+
<p><b>Aastha Jhunjhunwala, NVIDIA; Mark Moyou, NVIDIA</b><b><br />+
</b><b>October 20, 12:20–12:45 p.m. | LL20AB | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session deconstructs five open source vision-language model architectures, covering image tokenization, vision-language fusion, differences between training and inference, fine-tuning, and multi-GPU training.</span></p>+
<p><span style="font-weight: 400;">For production serving, the speakers cover image-token growth, KV-cache pressure, throughput, and where tools including vLLM fit.</span></p>+
<h4><b>Sponsored: Hardware-Aware AI: Building Agentic Systems from Cloud to Edge with PyTorch, ExecuTorch</b></h4>+
<p><b>Kavya Sri Chennoju, Arm</b><b><br />+
</b><b>October 20, 12:20–12:45 p.m. | LL20CD | Sponsored Session</b></p>+
<p><span style="font-weight: 400;">This session presents a cloud-to-edge workflow combining PyTorch for model development, ExecuTorch for on-device inference, vLLM for scalable LLM serving, and Arm Device Connect for interaction with heterogeneous hardware.</span></p>+
<p><span style="font-weight: 400;">The live workflow shows foundation models reasoning about tasks, invoking edge models, retrieving live sensor data, and coordinating physical devices.</span></p>+
<h4><b>Keeping GPUs Busy: High-Speed Storage for PyTorch via fsspec</b></h4>+
<p><b>Ankita Luthra, Google; Trinadh Kotturu, Google</b><b><br />+
</b><b>October 20, 3:40–3:50 p.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk presents Rapid Storage, which brings Google’s Colossus stateful protocol to PyTorch through </span><span style="font-weight: 400;">fsspec</span><span style="font-weight: 400;"> and uses persistent gRPC streams to the storage layer.</span></p>+
<p><span style="font-weight: 400;">The speakers report less than 1 ms random read/write latency, 20x faster data access, 6 TB/s of aggregate throughput, and 10x lower tail latency for random I/O. The integration extends through </span><span style="font-weight: 400;">gcsfs</span><span style="font-wei…+
<h4><b>Sponsored: From Prompt to Physical Action: A Live Hardware-Aware AI Demo with PyTorch, ExecuTorch</b></h4>+
<p><b>Kavya Sri Chennoju, Arm</b><b><br />+
</b><b>October 20, 3:55–4:05 p.m. | Community Expo | Demo Theater</b></p>+
<p><span style="font-weight: 400;">This live demonstration combines PyTorch, ExecuTorch, vLLM, and Arm Device Connect in a workflow spanning cloud, edge, and embedded devices.</span></p>+
<p><span style="font-weight: 400;">Starting with a natural-language request, a large language model reasons about the task, discovers available devices, invokes edge AI models, retrieves live sensor data, and coordinates hardware through a unified programming model.</span></p>+
<h4><b>From PyTorch to Production: Serving a Physics-Constrained Generative Model with ONNX, Ray, and vLLM</b></h4>+
<p><b>Arun Sharma, University of Minnesota</b><b><br />+
</b><b>October 21, 2:50–3:15 p.m. | 210AE | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session follows a physics-constrained generative downscaling model from PyTorch training into a served stack.</span></p>+
<p><span style="font-weight: 400;">The talk covers model export through </span><span style="font-weight: 400;">torch.onnx</span><span style="font-weight: 400;"> and AOTInductor, rectified-flow sampling, physics constraints at inference, and a Ray Train recipe for scaling. The serving path combines O…+
<h3><b>vLLM Community and Contribution</b></h3>+
<h4><b>Contributing to Inference OSS That Won’t Stand Still: A BoF on vLLM, llm-d, and the Moving Target</b></h4>+
<p><b>Maroon Ayoub, Red Hat; Nili Guy, IBM</b><b><br />+
</b><b>October 21, 10:35–11:05 a.m. | Community Expo | Birds of a Feather</b></p>+
<p><span style="font-weight: 400;">This Birds of a Feather session focuses on contributing to fast-moving inference projects including vLLM and llm-d.</span></p>+
<p><span style="font-weight: 400;">Contributors, maintainers, and prospective contributors will compare approaches to landing a first pull request, onboarding contributors, following technical decisions across project channels, and participating in cross-company open source development.</span></p>+
<h3><b>Explore the Full Program</b></h3>+
<p><span style="font-weight: 400;">These sessions include both talks centered directly on vLLM and broader sessions where vLLM is part of the serving stack, implementation, hardware integration, optimization work, or application workflow.</span></p>+
<p><a href="https://hubs.ly/Q04tDx8f0"><span style="font-weight: 400;">View the full conference schedule</span></a></p>+
<p><a href="https://hubs.ly/Q04tDw_W0"><span style="font-weight: 400;">Register for PyTorch Conference North America 2026</span></a></p>+
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<item>+
<title>Core PyTorch Sessions at PyTorch Conference North America 2026</title>+
<link>https://pytorch.org/blog/core-pytorch-sessions-at-pytorch-conference-north-america-2026/</link>+
+
<dc:creator><![CDATA[PyTorch Foundation]]></dc:creator>+
<pubDate>Thu, 27 Aug 2026 20:49:08 +0000</pubDate>+
<category><![CDATA[Announcements]]></category>+
<category><![CDATA[Blog]]></category>+
<category><![CDATA[PyTorch Conference]]></category>+
<category><![CDATA[PyTorch Conference North America]]></category>+
<guid isPermaLink="false">https://pytorch.org/?p=159992</guid>+
+
<description><![CDATA[TL;DR PyTorch Conference North America 2026 features Core PyTorch sessions spanning compiler and runtime work, distributed communication, device portability, release engineering, CI, observability, accelerator integration, and contributor infrastructure. Core PyTorch...]]>…+
<content:encoded><![CDATA[<h2><b>TL;DR</b></h2>+
<p><span style="font-weight: 400;">PyTorch Conference North America 2026 features Core PyTorch sessions spanning compiler and runtime work, distributed communication, device portability, release engineering, CI, observability, accelerator integration, and contributor infrastructure.</span></p>+
<h3><b>Core PyTorch at #PyTorchCon NA:</b></h3>+
<p><span style="font-weight: 400;">PyTorch Conference North America 2026 comes to San Jose, CA, October 20–21, with two days of technical talks, workshops, and discussions across the open source AI stack.</span></p>+
<p><span style="font-weight: 400;">Our Core PyTorch program gets into the machinery of the framework: compiler and runtime internals, distributed communication, device abstractions, hardware integration, release engineering, CI, profiling, and compatibility. The sessions below cover the APIs, implem…+
<p><a href="https://hubs.ly/Q04tDx8f0"><span style="font-weight: 400;">View the full conference schedule</span></a></p>+
<p><a href="https://hubs.ly/Q04tDw_W0"><span style="font-weight: 400;">Register for PyTorch Conference North America 2026 by September 4 to save on your ticket</span></a></p>+
<h3><b>Release Engineering, Compatibility, and Contributor Infrastructure</b></h3>+
<h4><b>Relay and Reuse: The Dual Engine Behind PyTorch Out-of-Tree Release Readiness</b></h4>+
<p><b>Jiahao Chen, Huawei; Jiahao Tan, Huawei</b><b><br />+
</b><b>October 20, 11:10–11:35 a.m. | LL21DEF | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session explains how an out-of-tree accelerator backend uses device-agnostic test reuse and cross-repository CI to keep pace with PyTorch releases. The speakers say </span><span style="font-weight: 400;">instantiate_device_type_tests</span><span style="font-we…+
<p><span style="font-weight: 400;">Together, the approach supports stable out-of-tree backend releases within 30 days of each upstream update.</span></p>+
<h4><b>Shipping PyTorch and Its Ecosystem: A Modern Release Story</b></h4>+
<p><b>Andrey Talman, Meta</b><b><br />+
</b><b>October 20, 11:45–11:55 a.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk covers changes to PyTorch release engineering across three areas: a faster and more predictable release process; continuous validation of Triton and vLLM against PyTorch nightlies so breakage surfaces upstream early; and AI agents that triage CI, separate…+
<p><span style="font-weight: 400;">The session also examines where agents accelerate release work and where humans still make the call.</span></p>+
<h4><b>Scaling PyTorch’s Compatibility Promise: A Tiered Cross-Repository CI Relay for Out-of-Tree Backends</b></h4>+
<p><b>Subin George, Red Hat LLC; Jewel K M, Red Hat</b><b><br />+
</b><b>October 20, 12:00–12:10 p.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk presents the Cross-Repository CI Relay, or CRCR, which forwards PyTorch PR and push events to downstream repositories in real time for compatibility validation before merge. It covers a four-tier trust model ranging from event dispatch through blocking me…+
<p><span style="font-weight: 400;">The speakers report that deployment with Ascend NPU and RISC-V backends reduces breakage detection from days to minutes.</span></p>+
<h4><b>Fighting Agents with Agents Bringing Claude to PyTorch CI, triage, and PR review</b></h4>+
<p><b>Driss Guessous, Meta</b><b><br />+
</b><b>October 20, 12:35–12:45 p.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">PyTorch maintainers are reviewing an increasing number of PRs written by AI agents. This talk covers how Claude was added to PyTorch infrastructure through </span><span style="font-weight: 400;">@claude</span><span style="font-weight: 400;"> on issues and PRs, auto…+
<p><span style="font-weight: 400;">The session also covers Bedrock/OIDC setup, two-stage GitHub Actions, tool allowlists, and repository-specific skills, with the stated goal of supporting maintainers rather than replacing them.</span></p>+
<h4><b>Clearing the Path Towards an ABI Stable PyTorch C++ Extension Ecosystem</b></h4>+
<p><b>Sean McGovern, Red Hat; Chris Leonard, Red Hat; Jane Xu, Meta</b><b><br />+
</b><b>October 21, 2:15–2:40 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">PyTorch’s stable ABI provides a binary-compatible C interface that extensions can target across PyTorch versions without recompilation. This session presents tools for identifying and inventorying unstable API usage and applying source-to-source conversion, w…+
<p><span style="font-weight: 400;">The speakers demonstrate the process on libraries including vLLM and SGLang.</span></p>+
<h3><b>Compiler, Runtime, Tensor, and Observability Work</b></h3>+
<h4><b>Beyond Size and Stride: Unleash Performance with Device-Aware Tensor Layouts</b></h4>+
<p><b>Olivier Tardieu, IBM; Matthew Arnold, IBM Research</b><b><br />+
</b><b>October 20, 4:20–4:30 p.m. | LL20AB | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">PyTorch tensors encode size, stride, and storage offset, but the speakers argue that these fields are insufficient to capture hardware layouts required by modern accelerators. This session introduces a tensor layout extension for device-aware specialization, includ…+
<p><span style="font-weight: 400;">The speakers also demonstrate how torch.compile and Inductor can use these controls to adapt layouts to the target device and adjust computations.</span></p>+
<h4><b>Observability Tooling for Cudagraph Workloads</b></h4>+
<p><b>Natalia Gimelshein, Meta; Driss Guessous, Meta</b><b><br />+
</b><b>October 20, 4:20–4:30 p.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">Cudagraph workloads can make profiling, stream visualization, and memory tracking difficult. This talk covers PyTorch utilities for using information captured during graph capture to enrich runtime information collected during replay.</span></p>+
<p><span style="font-weight: 400;">The goal is more information-rich performance and memory monitoring at low overhead, including nearly zero-overhead always-on monitoring.</span></p>+
<h4><b>Nested Graph Breaks: Reducing the Cost of Graph Breaks in torch.compile</b></h4>+
<p><b>William Wen, Meta</b><b><br />+
</b><b>October 20, 4:35–4:45 p.m. | LL20AB | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">A nested graph break previously caused O(N) duplicate graph breaks, O(N) graphs to be traced, and O(N²) frame traces for a function call O(N) layers deep.</span></p>+
<p><span style="font-weight: 400;">This session presents nested graph break support in Dynamo, reducing those costs to O(1) duplicate graph breaks, O(1) graphs traced, and O(N) frame traces. The speakers report larger captured graphs, fewer graph breaks, reduced Dynamo trace time, and improved debug…+
<h4><b>Static Tensor Shape Checking for PyTorch with Pyrefly</b></h4>+
<p><b>Steven Troxler, Meta Platforms; Avik Chaudhuri, Meta</b><b><br />+
</b><b>October 20, 5:30–5:55 p.m. | LL20AB | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session presents static tensor shape checking in the Pyrefly type checker, including inline tensor-shape hints and detection of mismatches before execution.</span></p>+
<p><span style="font-weight: 400;">The speakers cover symbolic integers, </span><span style="font-weight: 400;">Tensor</span><span style="font-weight: 400;"> and </span><span style="font-weight: 400;">Dim</span><span style="font-weight: 400;"> types, a shape-transform DSL, evaluation across 28 model…+
<h4><b>TorchInsights: Zero-GPU Memory & Runtime Estimation for Distributed Training and Agentic Research</b></h4>+
<p><b>Sanket Jayant Purandare, Meta; Aditya Venkataraman, Meta</b><b><br />+
</b><b>October 20, 5:45–5:55 p.m. | LL21ABC | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">TorchInsights estimates memory use and runtime for distributed training without running workloads on GPUs. Using fake tensors and fake execution, it can break down peak memory, sweep training configurations, rank parallelism plans, and simulate multi-stream GPU exe…+
<p><span style="font-weight: 400;">The tool uses pluggable cost models and is also presented as a lower-cost evaluation loop for AI-agent auto-research before spending real GPU time.</span></p>+
<h4><b>Parametrized Dynamic Shape CUDA Graphs</b></h4>+
<p><b>Elias Ellison, Meta; Daniel Galvez, NVIDIA</b><b><br />+
</b><b>October 21, 11:45 a.m.–12:10 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">Dynamic workloads can require padding, on-device shapes, repeated recordings, or larger model changes to use CUDA Graphs. This session combines parametrized CUDA Graphs with torch.compile’s symbolic tracing and guard infrastructure to capture and re-parametri…+
<p><span style="font-weight: 400;">The speakers report performance wins and reduced cold-start times for inference serving.</span></p>+
<h4><b>Native DSL Operators in PyTorch Core</b></h4>+
<p><b>Simon Layton, Meta</b><b><br />+
</b><b>October 21, 2:50–3:15 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">DSL-authored kernels have largely remained outside PyTorch core. This talk presents work toward adding DSL-authored operators as first-class citizens of PyTorch core, tying them into dispatch and testing.</span></p>+
<p><span style="font-weight: 400;">The work is intended to support new operators, highly optimized implementations, and targeted fixes for specialized performance cliffs.</span></p>+
<h4><b>From Backed to Unbacked: Sound, Predictable, and Controllable Dynamic Shapes in PyTorch</b></h4>+
<p><b>Laith Sakka, Meta</b><b><br />+
</b><b>October 21, 4:20–4:45 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">Backed dynamic shapes use symbolic sizes together with example-input hints and guards, which can allow recompilation. For workflows including vLLM, export, pre-compilation, and JIT deployments where dynamic-shape recompilation is not acceptable, this talk presents …+
<p><span style="font-weight: 400;">The session covers data-dependent errors and branching, work to close the performance gap with backed shapes across TorchBench and vLLM, and APIs for shape constraints and dispatch across compiled artifacts.</span></p>+
<h4 class="PDq2pG_selectionAnchorContainer" data-start="0" data-end="52"><span role="text"><strong data-start="5" data-end="52">Speeding Up torch.compile: A New FakeTensor</strong></span></h4>+
<p data-start="54" data-end="132"><strong data-start="54" data-end="72">Angel Li, Meta</strong><br data-start="72" data-end="75" /><strong data-start="75" data-end="132">October 21, 4:55–5:05 p.m. | LL21ABC | Lightning Talk</strong></p>+
<p data-start="134" data-end="308">FakeTensor is a lightweight substitute for regular tensors used by Dynamo and Inductor when building FX graphs, but its propagation contributes to torch.compile tracing time.</p>+
<p data-start="310" data-end="666">The speaker reports that one FakeTensor propagation takes around 20% of total Dynamo tracing time and that <code data-start="417" data-end="426">aten.mm</code> takes around 225 microseconds with a Python FakeTensor, while a C++ FakeTensor shows a 30x speedup for th…+
<h4><b>Lightweight FX Tracing in PyTorch</b></h4>+
<p><b>Richard Zou, Meta; Yidi Wu, Meta Inc.</b><b><br />+
</b><b>October 21, 5:10–5:20 p.m. | LL21ABC | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">Dynamo traces Python bytecode and can fall back to graph breaks, but the speakers say they have received feedback that Dynamo is too heavy for use cases where users require a full graph.</span></p>+
<p><span style="font-weight: 400;">This talk presents a lightweight FX tracer based on </span><span style="font-weight: 400;">make_fx</span><span style="font-weight: 400;"> for functionally pure PyTorch code. It covers the API, its guarantees, how it differs from Dynamo, and how it interacts with ot…+
<h3><b>Distributed Communication and Device Portability</b></h3>+
<h4><b>PyTorch Generalization: A Journey Toward Write Once, Run Anywhere</b></h4>+
<p><b>Yu Guangye, Intel; Eikan Wang, Intel</b><b><br />+
</b><b>October 20, 12:20–12:30 p.m. | LL21DEF | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">This talk covers ongoing work to make PyTorch APIs, runtime interfaces, and testing infrastructure less backend-specific. The speakers focus on model-level API unification across Autocast, Inductor, and graph capture and replay; </span><span style="font-weight: 400…+
<p><span style="font-weight: 400;">The stated goal is a consistent user and developer experience across in-tree and out-of-tree backends.</span></p>+
<h4><b>Future of Distributed Communication in PyTorch: New APIs for Fault Tolerance, RDMA and Extensibility</b></h4>+
<p><b>Tristan Rice, Meta; Kapil Sharma, Meta</b><b><br />+
</b><b>October 20, 4:20–4:45 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This talk presents new APIs for fault tolerance, one-sided RDMA, collective hooks, backend extensibility, and backend interfaces. Examples include </span><span style="font-weight: 400;">torch.distributed.reconfigure()</span><span style="font-weight: 400;"> for live…+
<p><span style="font-weight: 400;">The speakers say these features were incubated in TorchComms and are now being upstreamed into </span><span style="font-weight: 400;">torch.distributed</span><span style="font-weight: 400;">.</span></p>+
<h4 class="PDq2pG_selectionAnchorContainer" data-start="668" data-end="726"><span role="text"><strong data-start="673" data-end="726">rocSHMEM Symmetric Memory in PyTorch for AMD GPUs</strong></span></h4>+
<p data-start="728" data-end="809"><strong data-start="728" data-end="749">Prachi Gupta, AMD</strong><br data-start="749" data-end="752" /><strong data-start="752" data-end="809">October 20, 4:35–4:45 p.m. | LL21DEF | Lightning Talk</strong></p>+
<p data-start="811" data-end="1062">PyTorch symmetric memory issues communication from within device kernels, including Triton, allowing communication to overlap with computation. This talk covers extending that capability to AMD GPUs through rocSHMEM, now available in upstream PyTorch.</p>+
<p data-start="1064" data-end="1380">The session covers rocSHMEM device-side OpenSHMEM primitives exposed as Triton-callable operations, AMD-specific device-bitcode linking and HIP-module initialization behind a backend-agnostic layer shared with NVSHMEM, and a comparison with RCCL host-driven all-t…+
<h4><b>XCCL: Scaling PyTorch Collectives to Exascale on Intel GPUs with TorchComms</b></h4>+
<p><b>Panagiotis Kourdis, Intel; Tanima Dey, Intel Corporation</b><b><br />+
</b><b>October 20, 5:10–5:20 p.m. | LL21ABC | Lightning Talk</b></p>+
<p><span style="font-weight: 400;">XCCL adds native Intel GPU support to TorchComms through an in-tree backend built on Intel’s oneCCL library.</span></p>+
<p><span style="font-weight: 400;">The speakers report over 90% scaling efficiency across thousands of nodes on Argonne National Laboratory’s Aurora system while running TorchTitan and other AI workloads. The talk also covers a stream-ordered asynchronous execution model, differences between P…+
<h4><b>Introducing NCCL Extensions: Communication Patterns for Modern AI</b></h4>+
<p><b>Sreeram Potluri, NVIDIA; Artem Polyakov, NVIDIA</b><b><br />+
</b><b>October 21, 4:55–5:20 p.m. | 210AE | Breakout Session</b></p>+
<p><span style="font-weight: 400;">NCCL domain extensions are specialized libraries built on NCCL Device APIs for emerging communication patterns. This session introduces NCCL-EP for Mixture-of-Experts dispatch and combine and NCCL-M2N for zero-copy resharding between disjoint device meshes.</span><…+
<p><span style="font-weight: 400;">The speakers cover their design rationale, APIs, and performance results, including the use of NCCL-M2N to move weight snapshots from trainers to inference replicas for reinforcement learning rollout without CPU staging.</span></p>+
<h3><b>Accelerator Integration and Hardware-Aware Tooling</b></h3>+
<h4><b>Integrating the IBM Spyre Accelerator</b></h4>+
<p><b>David Grove, IBM; Antoni Viros Martin, IBM Research; Avery Blanchard, IBM Research</b><b><br />+
</b><b>October 20, 4:55–5:20 p.m. | LL21DEF | Breakout Session</b></p>+
<p><span style="font-weight: 400;">Torch-Spyre is an open source project that provides a PyTorch PrivateUse1 device with OpenReg, including an Inductor backend, for the IBM Spyre Accelerator.</span></p>+
<p><span style="font-weight: 400;">The talk covers the state of Torch-Spyre, functional enablement and performance improvements made in 2026, and contributions made back to PyTorch. It also discusses device-specific tensor layouts and scratchpad-optimized tiling, with an emphasis on integration with…+
<h4 class="PDq2pG_selectionAnchorContainer" data-start="1382" data-end="1440"><span role="text"><strong data-start="1387" data-end="1440">TorchTPU: Running PyTorch Natively on Google TPUs</strong></span></h4>+
<p class="" data-start="1442" data-end="1532"><strong data-start="1442" data-end="1468">Claudio Basile, Google</strong><br data-start="1468" data-end="1471" /><strong data-start="1471" data-end="1532">October 21, 11:10–11:35 a.m. | LL21ABC | Breakout Session</strong></p>+
<p data-start="1534" data-end="1850">This session presents TorchTPU as a high-performance, native PyTorch backend for Google TPUs. It covers an eager-first stack with ATen-to-StableHLO lowering and “DeferAndFuse” execution, an XLA stack that uses SparseCore for compute-communication over…+
<p data-start="1852" data-end="2045" data-is-last-node="" data-is-only-node="">The speaker reports production-scale engagements with private preview partners and describes TorchTPU as transitioning to an open source model, with a public GitHub repository release upcoming.</p>+
<h4><b>From torch.profiler to Hardware Cycles: A Practical Profiling Playbook for AWS Trainium</b></h4>+
<p><b>Esha Lakhotia, AWS Annapurna Labs; Pinak Panigrahi, Amazon</b><b><br />+
</b><b>October 21, 12:20–12:45 p.m. | LL21ABC | Breakout Session</b></p>+
<p><span style="font-weight: 400;">This session shows how the </span><span style="font-weight: 400;">torch.profiler</span><span style="font-weight: 400;"> API can be used on AWS Trainium without code changes or separate tooling, from CPU dispatch and runtime orchestration down to on-device hardware …+
<p><span style="font-weight: 400;">The speakers walk through tracing slow model components to compiled operations and Python source, using cycle-level device timelines to identify bottlenecks, and AI-assisted analysis that identifies performance bottlenecks and suggests potential fixes.</span></p>+
<h3><b>Explore the Full Program</b></h3>+
<p><span style="font-weight: 400;">These sessions represent part of our Core PyTorch program across October 20 and 21. Explore the full PyTorch Conference North America program for additional sessions across training, inference, applications, kernel engineering, responsible AI, and more.</span></p>+
<p><a href="https://hubs.ly/Q04tDx8f0"><span style="font-weight: 400;">View the full conference schedule</span></a></p>+
<p><a href="https://hubs.ly/Q04tDw_W0"><span style="font-weight: 400;">Register for PyTorch Conference North America 2026</span></a></p>+
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<title>PyTorch Ecosystem Landscape Welcomes Perforated, AReaL, TorchJD, RLinf, Miles, SMG, FiftyOne, TokenSpeed, VisualTorch, and TorchSurv</title>+
<link>https://pytorch.org/blog/pytorch-ecosystem-landscape-q3-update/</link>+
+
<dc:creator><![CDATA[PyTorch Foundation]]></dc:creator>+
<pubDate>Wed, 26 Aug 2026 20:53:37 +0000</pubDate>+
<category><![CDATA[Announcements]]></category>+
<category><![CDATA[Blog]]></category>+
<guid isPermaLink="false">https://pytorch.org/?p=159483</guid>+
+
<description><![CDATA[The PyTorch Ecosystem Working Group is happy to welcome 10 new projects to the PyTorch Ecosystem Landscape including Perforated, AReaL, TorchJD, RLinf, Miles, SMG, FiftyOne, TokenSpeed, VisualTorch, and TorchSurv. The...]]></description>+
<content:encoded><![CDATA[<p><span style="font-weight: 400;">The PyTorch Ecosystem Working Group is happy to welcome 10 new projects to the PyTorch Ecosystem Landscape including Perforated, AReaL, TorchJD, RLinf, Miles, SMG, FiftyOne, TokenSpeed, VisualTorch, and TorchSurv. The </span><a h…+
<h2><span style="font-weight: 400;">New Additions to the PyTorch Ecosystem</span></h2>+
<h3><span style="font-weight: 400;">Perforated</span></h3>+
<p><span style="font-weight: 400;">Perforated is a data-efficiency library for PyTorch that improves model performance by adding neuron-specific reinforcement learning signals during training. Originally inspired by a breakthrough in neuroscience research, Perforated applies a lightweight modificati…+
<p><span style="font-weight: 400;">Implemented entirely in Python using standard PyTorch functionality, Perforated is proud to be officially welcomed to the PyTorch ecosystem. Teams can evaluate Perforated against their current models and benchmarks with minimal integration effort, making it easy to…+
<p><span style="font-weight: 400;">Learn more at </span><a href="http://perforatedai.com"><span style="font-weight: 400;">perforatedai.com</span></a><span style="font-weight: 400;">. Find us on </span><a href="https://github.com/PerforatedAI/PerforatedAI"><span style="font-weight: 400;">Github</span…+
<h3><span style="font-weight: 400;">AReaL</span></h3>+
<p><span style="font-weight: 400;">AReaL is an open source, modular RL infrastructure that bridges foundation model training with modern LLM/VLM-based agent applications. Built on a fully asynchronous RL training paradigm, AReaL enables seamless building, deployment, evaluation, and fine tuning of a…+
<p><span style="font-weight: 400;">AReaL decomposes RL into independent, composable services, enabling flexible scaling, fault tolerance, and independent optimization of system components. This design also allows broad integration with diverse training and inference backends, including vLLM, SGLang,…+
<p><span style="font-weight: 400;">Learn more about </span><a href="https://github.com/inclusionAI/AReaL"><span style="font-weight: 400;">AReaL</span></a><span style="font-weight: 400;">.</span></p>+
<h3><span style="font-weight: 400;">TorchJD</span></h3>+
<p><span style="font-weight: 400;">TorchJD is a library to train neural networks with multiple losses. Two main classes of methods are supported:</span></p>+
<ul>+
<li style="font-weight: 400;" aria-level="1"><span style="font-weight: 400;">scalarization: combine the losses into a single scalar loss, and minimize it with a gradient-based optimizer.</span></li>+
<li style="font-weight: 400;" aria-level="1"><span style="font-weight: 400;">Jacobian Descent (JD): compute the Jacobian of the vector of losses (one gradient per loss), and aggregate it into a common update direction to feed to the optimizer.</span></li>+
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